1. Field of the Invention
The present invention relates to electronic memories and, more particularly, to memory devices and methods for performing hidden-refreshing of volatile memory elements.
2. State of the Art
Memory cells, and in particular dynamic random access memory (DRAM) cells, need to be refreshed from time-to-time to restore leaking charge and thus maintain a logic state therein. Conventionally, a DRAM refresh process is initiated by a processor or controller coupled to the memory device by supplying an appropriate control signal to a command or control interface of the memory device. More recently, DRAMs hide some forms of refresh from the processor.
In contrast to dynamic memory devices that require periodic refreshing of the memory cells, static memory devices that do not require refreshing of the memory cells have also become commonplace. However, static random access memory (SRAM) devices require more transistors and circuitry to maintain the stored charge. Because of the additional circuitry and the increased area associated therewith, design tradeoffs are frequently undertaken to determine an appropriate form of memory for a system. One developing form of a hybrid memory device has become known as a pseudo static random access memory (PSRAM) device. Accordingly, a PSRAM device includes desirable characteristics of both DRAM devices and SRAM devices, namely, the low cost and large capacity of a DRAM device with the simplified interface and integration of an SRAM device. The PSRAM device provides an improved memory cell density by employing higher density dynamic memory cells but also requires periodic refreshing in order to maintain the stored charge at levels sufficient to determine the logic state stored therein.
To accommodate these refresh requirements, PSRAM devices incorporate refresh circuitry which is “hidden” within the memory device and thus relieves the system designer of the burden of programming a controller or processor to periodically execute the refresh process. This hidden-refresh process within PSRAM devices must be periodically performed within the PSRAM device and requires the use of an appreciable amount of power delivered to the PSRAM device for executing the necessary refresh operation. Because power management is generally of great importance for systems that integrate memory devices, there is a need to provide an improved power conservation methodology for systems that integrate memory devices that utilize hidden-refresh techniques.